Programmable logic chips of conventional logic devices such as, in particular, processors, execute programs which are loaded from a memory. The software to be executed, in the form of instruction words, is stored there as machine instruction. These instruction words are loaded, analyzed, interpreted and executed in a processing unit. In this arrangement, the processing of a single instruction word triggers a multiplicity of individual actions in the logic device.
The basic structure and organization of known digital logic devices, particularly of computers with microprocessors, is based on the concept of the so-called “von Neumann computer”. In its minimum configuration, its Central Processing Unit CPU, i.e. its computer core, comprises a main memory, a control unit and a processing unit (or arithmetic/logic unit) as main components:                The main memory stores instruction words (program data) and processing data (operant words) and provides these on request. The main memory also stores intermediate and end results of the processing. Main memories can be implemented by volatile or non-volatile memories.        The control unit organizes the order in which the instruction words are processed. It requests instruction words from the main memory and causes them to be executed in the processing unit. In addition, it analyzes the instruction words and causes processing data to be delivered to the processing unit.        The processing unit executes the operation on the processing data and supplies corresponding result words to the main memory. For each operation, the processing unit contains a microprogram which enables the transmission paths needed. The processing unit is set by the control unit to the respective type of operation, i.e. to the instruction to be processed. The central processing unit is associated with peripheral devices which can be external memories and input and output devices. The specified main components of the central processing unit can be physically separate; in most cases, however, they are implemented on a common processor chip with a cache or, for example, an embedded ROM.        
Looking at the programming of such a Programmable Logic Device (PLD) with the above-mentioned basic components of the von Neumann computer in greater detail shows that the program and the initialization data are accommodated in inexpensive memories (having a minimum of 1 transistor per memory cell) and are executed into the CPU only when it is their turn. The inexpensive storage, on the one hand, and the “reuse” of the more elaborate CPU circuits such as ALU (Arithmetic Logic Unit) for all possible instructions, on the other hand, are the positive contributions to a so-called “functional density” of the processor-based computers. Naturally, the sequence of processing in time provides a negative contribution. The functional density can be defined as the mean number of active gate equivalents per silicon area and time.
In known programmable logic devices (PLDs) with computing capacity, memory and Input/Output unit I/O as found, e.g. in the US-A document initially mentioned, their structure is programmed once and the program (and data) content is stored in the structure itself. This type of storage is complex because a quantity of additional transistors must be added around the memory itself for the purpose of quick conversion into switched data paths. Although only little information is available on the utilization of the silicon, factors of 20 to 40 in the ratio of total number/visible transistor capacity (in the sense of switching function) should be assumed. In the known embodiment of a logic device, the linking of its logic blocks is firstly related to the coupling of data outputs to data inputs (routing operation) and, secondly, to the processing of the input data to the output data in the individual logic blocks (logic operation). The routing operation applies both to data which come from logic blocks (logic elements) or are conducted into these, and to those which come from I/O pads or are conducted into these. In this system of the known embodiment, only data coupling has been considered.
In U.S. Pat. No. 6,333,641 B1, a programmable logic device with an array of logic modules or blocks is found. A connecting unit with vertical routing tracks, horizontal routing tracks and local routing tracks links the logic blocks. A (universal) omnibus (data exchange bus) is placed over the array which is linked to the array in such a manner that it dynamically forms independent subarrays of the logic blocks with variable size which, in turn, are connected to the omnibus. The linking is specified from the start. This, too, is a matter of data connections, i.e. an exchange of data, as in the case of U.S. Pat. No. 4,870,302 A.
Since the programmability in the form of a memory with conversion into switched data paths is quite expensive as in the case of the computer, but the complete program has hitherto been stored in a chip, the PLDs, in spite of a potential for high functional density, “only” achieve a factor of 10 more than processors. This means that the gain in speed in PLDs compared with processor solutions comes at a high price.